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3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers description the 3850 group (spec. h) is the 8-bit microcomputer based on the 740 family core technology. the 3850 group (spec. h) is designed for the household products and office automation equipment and includes serial i/o functions, 8-bit timer, and a-d converter. features l basic machine-language instructions ...................................... 71 l minimum instruction execution time .................................. 0.5 m s (at 8 mhz oscillation frequency) l memory size rom ................................................................... 8k to 32k bytes ram ................................................................. 512 to 1024 bytes l programmable input/output ports ............................................ 34 l interrupts ................................................. 14 sources, 14 vectors l timers ............................................................................. 8-bit 5 4 l serial i/o1 .................... 8-bit 5 1(uart or clock-synchronized) l serial i/o2 ................................... 8-bit 5 1(clock-synchronized) l pwm ............................................................................... 8-bit 5 1 l a-d converter ............................................... 10-bit 5 5 channels l watchdog timer ............................................................ 16-bit 5 1 l clock generating circuit ..................................... built-in 2 circuits (connect to external ceramic resonator or quartz-crystal oscillator) pin configuration (top view) fig. 1 m38503m4h-xxxfp/sp pin configuration l power source voltage in high-speed mode .................................................. 4.0 to 5.5 v (at 8 mhz oscillation frequency) in middle-speed mode ............................................... 2.7 to 5.5 v (at 8 mhz oscillation frequency) in low-speed mode .................................................... 2.7 to 5.5 v (at 32 khz oscillation frequency) l power dissipation in high-speed mode ..........................................................34 mw (at 8 mhz oscillation frequency, at 5 v power source voltage) in low-speed mode ............................................................ 60 m w (at 32 khz oscillation frequency, at 3 v power source voltage) l operating temperature range .................................... C20 to 85c application office automation equipment, fa equipment, household products, consumer electronics, etc. package type : fp ........................... 42p2r-a/e (42-pin plastic-molded ssop) package type : sp ........................... 42p4b (42-pin plastic-molded sdip) p 4 0 / c n t r 1 p 4 1 / i n t 0 p 4 2 / i n t 1 p 4 3 / i n t 2 / s c m p 2 a v s s p 4 4 / i n t 3 / p w m v r e f v c c p 0 0 / s i n 2 p 0 4 p 0 5 p 0 6 p 0 7 p 1 1 / ( l e d 1 ) p 1 2 / ( l e d 2 ) p 1 3 / ( l e d 3 ) p 1 4 / ( l e d 4 ) p 1 5 / ( l e d 5 ) p 1 0 / ( l e d 0 ) p 0 1 / s o u t 2 p 0 2 / s c l k 2 p 3 1 / a n 1 p 3 2 / a n 2 p 3 0 / a n 0 p 3 3 / a n 3 p 3 4 / a n 4 p 0 3 / s r d y 2 4 0 4 1 4 2 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 4 3 5 3 6 3 7 3 8 3 9 3 3 3 2 1 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 9 8 7 6 5 4 1 0 m 3 8 5 0 3 m 4 h - x x x f p m 3 8 5 0 3 m 4 h - x x x s p p 1 6 / ( l e d 6 ) p 1 7 / ( l e d 7 ) p 2 7 / c n t r 0 / s r d y 1 p 2 6 / s c l k p 2 5 / t x d p 2 4 / r x d p 2 3 p 2 2 c n v s s p 2 1 / x c i n p 2 0 / x c o u t r e s e t x i n x o u t v s s
2 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers functional block diagram fig. 2 functional block diagram functional block int 0 v ref av ss r a m r o m c p u a x y s pc h pc l ps v ss 21 reset 18 v cc 1 15 cnv ss 23 x in 19 20 si/o1(8) reset input clock generating circuit main-clock input main-clock output a-d converter (10) cntr 0 cntr 1 timer y( 8 ) timer x( 8 ) prescaler 12(8) prescaler x(8) prescaler y(8) timer 1( 8 ) timer 2( 8 ) sub-clock input x out x cin x cout sub-clock output watchdog timer reset p2(8) p3(5) i/o port p2 i/o port p3 p4(5) i/o port p4 int 3 4 6 8 5 7 39 41 38 40 42 9 11 13 17 10 12 14 16 p1(8) i/o port p1 22 24 26 28 23 25 27 29 p0(8) i/o port p0 30 31 32 33 34 35 36 37 pwm (8) x cin x cout si/o2(8)
3 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers v cc , v ss pin description functions name pin ?apply voltage of 2.7 v C 5.5 v to vcc, and 0 v to vss. ?this pin controls the operation mode of the chip. ?normally connected to v ss . ?reset input pin for active l. ?input and output pins for the clock generating circuit. ?connect a ceramic resonator or quartz-crystal oscillator between the x in and x out pins to set the oscillation frequency. ?when an external clock is used, connect the clock source to the x in pin and leave the x out pin open. ?8-bit cmos i/o port. ?i/o direction register allows each pin to be individually programmed as either input or output. ?cmos compatible input level. ?cmos 3-state output structure. ?p1 0 to p1 7 (8 bits) are enabled to output large current for led drive. power source table 1 pin description function except a port function clock input clock output i/o port p0 cnv ss input cnv ss reset reset input x in x out p0 0 /s in2 p0 1 /s out2 p0 2 /s clk2 p0 3 /s rdy2 p0 4 Cp0 7 i/o port p1 p1 0 Cp1 7 ? serial i/o2 function pin ? sub-clock generating circuit i/o pins (connect a resonator) i/o port p2 i/o port p3 i/o port p4 ?8-bit cmos i/o port. ?i/o direction register allows each pin to be individually programmed as either input or output. ?cmos compatible input level. ?p2 0 , p2 1 , p2 4 to p2 7 : cmos3-state output structure. ?p2 2 , p2 3 : n-channel open-drain structure. ? serial i/o1 function pin ? serial i/o1 function pin/ timer x function pin ? a-d converter input pin ? timer y function pin ? interrupt input pins ? interrupt input pin ? s cmp2 output pin ? interrupt input pin ? pwm output pin ?8-bit cmos i/o port with the same function as port p0. ?cmos compatible input level. ?cmos 3-state output structure. ?8-bit cmos i/o port with the same function as port p0. ?cmos compatible input level. ?cmos 3-state output structure. p2 0 /x cout p2 1 /x cin p2 2 p2 3 p2 4 /rxd p2 5 /txd p2 6 /s clk p2 7 /cntr 0 / s rdy1 p3 0 /an 0 C p3 4 /an 4 p4 0 /cntr 1 p4 1 /int 0 p4 2 /int 1 p4 3 /int 2 /s cmp2 p4 4 /int 3 /pwm
4 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers part numbering fig. 3 part numbering m 3 8 5 0 3 m 4 hC x x xs p p r o d u c t n a m e p a c k a g e t y p e s p : 4 2 p 4 b f p : 4 2 p 2 r - a / e s s : 4 2 s 1 b - a r o m n u m b e r o m i t t e d i n o n e t i m e p r o m v e r s i o n s h i p p e d i n b l a n k , e p r o m v e r s i o n , a n d f l a s h m e m o r y v e r s i o n . r o m / p r o m / f l a s h m e m o r y s i z e 1 2 3 4 5 6 7 8 : 4 0 9 6 b y t e s : 8 1 9 2 b y t e s : 1 2 2 8 8 b y t e s : 1 6 3 8 4 b y t e s : 2 0 4 8 0 b y t e s : 2 4 5 7 6 b y t e s : 2 8 6 7 2 b y t e s : 3 2 7 6 8 b y t e s t h e f i r s t 1 2 8 b y t e s a n d t h e l a s t 2 b y t e s o f r o m a r e r e s e r v e d a r e a s ; t h e y c a n n o t b e u s e d a s a u s e r s r o m a r e a . h o w e v e r , t h e y c a n b e p r o g r a m m e d o r e r a s e d i n t h e f l a s h m e m o r y v e r s i o n , s o t h a t t h e u s e r s c a n u s e t h e m . m e m o r y t y p e m: m a s k r o m v e r s i o n e : e p r o m o r o n e t i m e p r o m v e r s i o n f: f l a s h m e m o r y v e r s i o n r a m s i z e 0 1 2 3 4 : 1 9 2 b y t e s : 2 5 6 b y t e s : 3 8 4 b y t e s : 5 1 2 b y t e s : 6 4 0 b y t e s C : s t a n d a r d o m i t t e d i n o n e t i m e p r o m v e r s i o n s h i p p e d i n b l a n k , e p r o m v e r s i o n , a n d f l a s h m e m o r y v e r s i o n . h C : p a r t i a l s p e c i f i c a t i o n c h a n g e d v e r s i o n : 3 6 8 6 4 b y t e s : 4 0 9 6 0 b y t e s : 4 5 0 5 6 b y t e s : 4 9 1 5 2 b y t e s : 5 3 2 4 8 b y t e s : 5 7 3 4 4 b y t e s : 6 1 4 4 0 b y t e s 9 a b c d e f 5 6 7 8 9 : 7 6 8 b y t e s : 8 9 6 b y t e s : 1 0 2 4 b y t e s : 1 5 3 6 b y t e s : 2 0 4 8 b y t e s
5 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers group expansion mitsubishi plans to expand the 3850 group (spec. h) as follows. memory type support for mask rom, one time prom, and flash memory ver- sions. memory size flash memory size ......................................................... 32 k bytes one time prom size ..................................................... 24 k bytes mask rom size ................................................... 8 k to 32 k bytes ram size ............................................................... 512 to 1 k bytes packages 42p4b ......................................... 42-pin shrink plastic-molded dip 42p2r-a/e ........................................... 42-pin plastic-molded sop 42s1b-a .................. 42-pin shrink ceramic dip (eprom version) fig. 4 memory expansion plan memory expansion plan 3 2 k 2 8 k 2 4 k 2 0 k 1 6 k 1 2 k 8 k 3 8 45 1 26 4 07 6 88 9 61 0 2 4 1 1 5 21 2 8 01 4 0 81 5 3 62 0 4 8 r o m e x t e r a n a l r o m s i z e ( b y t e s ) r a m s i z e ( b y t e s ) a s o f f e b . 2 0 0 0 m 3 8 5 0 7 m 8 / f 8 m 3 8 5 0 4 m 6 / e 6 m 3 8 5 0 3 m 4 h m 3 8 5 0 3 m 2 h u n d e r d e v e l o p m e n t p r o d u c t s u n d e r d e v e l o p m e n t o r p l a n n i n g : t h e d e v e l o p m e n t s c h e d u l e a n d s p e c i f i c a t i o n m a y b e r e v i s e d w i t h o u t n o t i c e . t h e d e v e l o p m e n t o f pl a n n i n g p r o d u c t s m a y b e s t o p p e d . m a s s p r o d u c t i o n m a s s p r o d u c t i o n m a s s p r o d u c t i o n
6 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers currently planning products are listed below. ram size (bytes) remarks package table 2 support products product name as of feb. 2000 24576 (24446) rom size (bytes) rom size for user in ( ) m38503m2h-xxxsp m38503m2h-xxxfp m38503m4h-xxxsp m38503m4h-xxxfp m38504m6-xxxsp m38504e6-xxxsp m388504e6sp m388504e6ss m38504m6-xxxfp m38504e6-xxxfp m38504e6fp 42p4b 42p2r-a/e 424p4b 42p2r-a/e 424p4b 42s1b-a 42p2r-a/e mask rom version mask rom version mask rom version mask rom version mask rom version one time prom version one time prom version (blank) eprom version mask rom version one time prom version one time prom version (blank) 8192 (8062) 512 16384 (16254) 640 512 table 3 3850 group (standard) and 3850 group (spec. h) corresponding products 3850 group (standard) m38503m2-xxxfp/sp m38503m4-xxxfp/sp m38503e4-xxxfp/sp m38503e4fp/sp m38503e4ss 3850 group (spec. h) m38503m2h-xxxfp/sp m38503m4h-xxxfp/sp m38504m6-xxxfp/sp m38504e6-xxxfp/sp m38504e6fp/sp m38504e6ss m38507m8-xxxfp/sp m38507f8fp/sp table 4 differences between 3850 group (standard) and 3850 group (spec. h) serial i/o a-d converter large current port 3850 group (standard) 1: serial i/o (uart or clock-synchronized) unserviceable in low-speed mode 5: p1 3 Cp1 7 3850 group (spec. h) 2: serial i/o1 (uart or clock-synchronized) serial i/o2 (clock-synchronized) serviceable in low-speed mode 8: p1 0 Cp1 7 notes on differences between 3850 group (standard) and 3850 group (spec. h) (1) the absolute maximum ratings of 3850 group (spec. h) is smaller than that of 3850 group (standard). ?power source voltage vcc = C0.3 to 6.5 v ?cnvss input voltage v i = C0.3 to vcc +0.3 v (2) the oscillation circuit constants of x in -x out , x cin -x cout may be some differences between 3850 group (standard) and 3850 group (spec. h). (3) do not write any data to the reserved area and the reserved bit. (do not change the contents after rest.) (4) fix bit 3 of the cpu mode register to 1. (5) be sure to perform the termination of unused pins.
7 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers functional description central processing unit (cpu) the 3850 group (spec. h) uses the standard 740 family instruc- tion set. refer to the table of 740 family addressing modes and machine instructions or the 740 family software manual for de- tails on the instruction set. machine-resident 740 family instructions are as follows: the fst and slw instructions cannot be used. the stp, wit, mul, and div instructions can be used. [accumulator (a)] the accumulator is an 8-bit register. data operations such as data transfer, etc., are executed mainly through the accumulator. [index register x (x)] the index register x is an 8-bit register. in the index addressing modes, the value of the operand is added to the contents of register x and specifies the real address. [index register y (y)] the index register y is an 8-bit register. in partial instruction, the value of the operand is added to the contents of register y and specifies the real address. [stack pointer (s)] the stack pointer is an 8-bit register used during subroutine calls and interrupts. this register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. the low-order 8 bits of the stack address are determined by the contents of the stack pointer. the high-order 8 bits of the stack ad- dress are determined by the stack page selection bit. if the stack page selection bit is 0 , the high-order 8 bits becomes 00 16 . if the stack page selection bit is 1, the high-order 8 bits becomes 01 16 . the operations of pushing register contents onto the stack and popping them from the stack are shown in figure 6. store registers other than those described in figure 6 with pro- gram when the user needs them during interrupts or subroutine calls. [program counter (pc)] the program counter is a 16-bit counter consisting of two 8-bit registers pc h and pc l . it is used to indicate the address of the next instruction to be executed. fig. 5 740 family cpu register structure a accumulator b7 b7 b7 b7 b0 b7 b15 b0 b7 b0 b0 b0 b0 x index register x y index register y s stack pointer pc l program counter pc h n v t b d i z c processor status register (ps) carry flag zero flag interrupt disable flag decimal mode flag break flag index x mode flag overflow flag negative flag
8 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers table 5 push and pop instructions of accumulator or processor status register accumulator processor status register push instruction to stack pha php pop instruction from stack pla plp fig. 6 register push and pop at interrupt generation and subroutine call n o t e : c o n d i t i o n f o r a c c e p t a n c e o f a n i n t e r r u p t i n t e r r u p t e n a b l e f l a g i s 1 e x e c u t e j s r o n - g o i n g r o u t i n e m ( s )( p c h ) ( s ) ( s ) 1 m ( s )( p c l ) e x e c u t e r t s ( p c l )m ( s ) ( s ) ( s ) 1 ( s ) ( s ) + 1 ( s ) ( s ) + 1 ( p c h )m ( s ) s u b r o u t i n e p o p re t u r n a d d r e s s f r o m s t a c k p u s h r e t u r n a d d r e s s o n s t a c k m ( s )( p s ) e x e c u t e r t i ( p s )m ( s ) ( s ) ( s ) 1 ( s ) ( s ) + 1 i n t e r r u p t s e r v i c e r o u t i n e p o p c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r f r o m s t a c k m ( s )( p c h ) ( s ) ( s ) e 1 m ( s )( p c l ) ( s ) ( s ) e 1 ( p c l )m ( s ) ( s ) ( s ) + 1 ( s ) ( s ) + 1 ( p c h )m ( s ) p o p r e t u r n a d d r e s s f r o m s t a c k i f l a g i s s e t f r o m 0 t o 1 f e t c h t h e j u m p v e c t o r p u s h r e t u r n a d d r e s s o n s t a c k p u s h c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r o n s t a c k i n t e r r u p t r e q u e s t ( n o t e ) i n t e r r u p t d i s a b l e f l a g i s 0
9 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers [processor status register (ps)] the processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide mcu operation. branch opera- tions can be performed by testing the carry (c) flag , zero (z) flag, overflow (v) flag, or the negative (n) flag. in decimal mode, the z, v, n flags are not valid. ?bit 0: carry flag (c) the c flag contains a carry or borrow generated by the arithmetic logic unit (alu) immediately after an arithmetic operation. it can also be changed by a shift or rotate instruction. ?bit 1: zero flag (z) the z flag is set if the result of an immediate arithmetic operation or a data transfer is 0, and cleared if the result is anything other than 0. ?bit 2: interrupt disable flag (i) the i flag disables all interrupts except for the interrupt generated by the brk instruction. interrupts are disabled when the i flag is 1. ?bit 3: decimal mode flag (d) the d flag determines whether additions and subtractions are executed in binary or decimal. binary arithmetic is executed when this flag is 0; decimal arithmetic is executed when it is 1. decimal correction is automatic in decimal mode. only the adc and sbc instructions can be used for decimal arithmetic. ?bit 4: break flag (b) the b flag is used to indicate that the current interrupt was generated by the brk instruction. the brk flag in the processor status register is always 0. when the brk instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to 1. ?bit 5: index x mode flag (t) when the t flag is 0, arithmetic operations are performed between accumulator and memory. when the t flag is 1, direct arithmetic operations and direct data transfers are enabled between memory locations. ?bit 6: overflow flag (v) the v flag is used during the addition or subtraction of one byte of signed data. it is set if the result exceeds +127 to -128. when the bit instruction is executed, bit 6 of the memory location operated on by the bit instruction is stored in the overflow flag. ?bit 7: negative flag (n) the n flag is set if the result of an arithmetic operation or data transfer is negative. when the bit instruction is executed, bit 7 of the memory location operated on by the bit instruction is stored in the negative flag. table 6 set and clear instructions of each bit of processor status register set instruction clear instruction c flag z flag i flag d flag b flag t flag v flag n flag sec clc _ _ sei cli sed cld _ _ set clt clv _ _ _
10 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers [cpu mode register (cpum)] 003b 16 the cpu mode register contains the stack page selection bit, etc. the cpu mode register is allocated at address 003b 16 . fig. 7 structure of cpu mode register cpu mode register ( cpum : address 003b 16 ) b7 b0 stack page selection bit 0 : 0 page 1 : 1 page fix this bit to 1. processor mode bits b1 b0 0 0 : single-chip mode 0 1 : 1 0 : not available 1 1 : port x c switch bit 0 : i/o port function (stop oscillating) 1 : x cin Cx cout oscillating function main clock (x in Cx out ) stop bit 0 : oscillating 1 : stopped main clock division ratio selection bits b7 b6 0 0 : f = f(x in )/2 (high-speed mode) 0 1 : f = f(x in )/8 (middle-speed mode) 1 0 : f = f(x cin )/2 (low-speed mode) 1 1 : not available
11 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers memory special function register (sfr) area the special function register area in the zero page contains control registers such as i/o ports and timers. ram ram is used for data storage and for stack area of subroutine calls and interrupts. rom the first 128 bytes and the last 2 bytes of rom are reserved for device testing and the rest is user area for storing programs. interrupt vector area the interrupt vector area contains reset and interrupt vectors. zero page access to this area with only 2 bytes is possible in the zero page addressing mode. special page access to this area with only 2 bytes is possible in the special page addressing mode. fig. 8 memory map diagram 0100 16 0000 16 0040 16 ff00 16 ffdc 16 fffe 16 ffff 16 192 256 384 512 640 768 896 1024 1536 2048 xxxx 16 00ff 16 013f 16 01bf 16 023f 16 02bf 16 033f 16 03bf 16 043f 16 063f 16 083f 16 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 f000 16 e000 16 d000 16 c000 16 b000 16 a000 16 9000 16 8000 16 7000 16 6000 16 5000 16 4000 16 3000 16 2000 16 1000 16 f080 16 e080 16 d080 16 c080 16 b080 16 a080 16 9080 16 8080 16 7080 16 6080 16 5080 16 4080 16 3080 16 2080 16 1080 16 yyyy 16 zzzz 16 ram rom 0ff0 16 0fff 16 sfr area not used interrupt vector area rom area reserved rom area (128 bytes) zero page special page ram area ram size (bytes) address xxxx 16 rom size (bytes) address yyyy 16 reserved rom area address zzzz 16 not used sfr area (note) note: flash memory version only
12 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 9 memory map of special function register (sfr) 0 0 2 0 1 6 0 0 2 1 1 6 0 0 2 2 1 6 0 0 2 3 1 6 0 0 2 4 1 6 0 0 2 5 1 6 0 0 2 6 1 6 0 0 2 7 1 6 0 0 2 8 1 6 0 0 2 9 1 6 0 0 2 a 1 6 0 0 2 b 1 6 0 0 2 c 1 6 0 0 2 d 1 6 0 0 2 e 1 6 0 0 2 f 1 6 0 0 3 0 1 6 0 0 3 1 1 6 0 0 3 2 1 6 0 0 3 3 1 6 0 0 3 4 1 6 0 0 3 5 1 6 0 0 3 6 1 6 0 0 3 7 1 6 0 0 3 8 1 6 0 0 3 9 1 6 0 0 3 a 1 6 0 0 3 b 1 6 0 0 3 c 1 6 0 0 3 d 1 6 0 0 3 e 1 6 0 0 3 f 1 6 0 0 0 0 1 6 0 0 0 1 1 6 0 0 0 2 1 6 0 0 0 3 1 6 0 0 0 4 1 6 0 0 0 5 1 6 0 0 0 6 1 6 0 0 0 7 1 6 0 0 0 8 1 6 0 0 0 9 1 6 0 0 0 a 1 6 0 0 0 b 1 6 0 0 0 c 1 6 0 0 0 d 1 6 0 0 0 e 1 6 0 0 0 f 1 6 0 0 1 0 1 6 0 0 1 1 1 6 0 0 1 2 1 6 0 0 1 3 1 6 0 0 1 4 1 6 0 0 1 5 1 6 0 0 1 6 1 6 0 0 1 7 1 6 0 0 1 8 1 6 0 0 1 9 1 6 0 0 1 a 1 6 0 0 1 b 1 6 0 0 1 c 1 6 0 0 1 d 1 6 0 0 1 e 1 6 0 0 1 f 1 6 p o r t p 0 ( p 0 ) p o r t p 0 d i r e c t i o n r e g i s t e r ( p 0 d ) p o r t p 1 ( p 1 ) p o r t p 1 d i r e c t i o n r e g i s t e r ( p 1 d ) p o r t p 2 ( p 2 ) p o r t p 2 d i r e c t i o n r e g i s t e r ( p 2 d ) p o r t p 3 ( p 3 ) p o r t p 3 d i r e c t i o n r e g i s t e r ( p 3 d ) p o r t p 4 ( p 4 ) p o r t p 4 d i r e c t i o n r e g i s t e r ( p 4 d ) t r a n s m i t / r e c e i v e b u f f e r r e g i s t e r ( t b / r b ) s e r i a l i / o 1 s t a t u s r e g i s t e r ( s i o s t s ) s e r i a l i / o 1 c o n t r o l r e g i s t e r ( s i o c o n ) u a r t c o n t r o l r e g i s t e r ( u a r t c o n ) b a u d r a t e g e n e r a t o r ( b r g ) i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) a - d c o n v e r s i o n l o w - o r d e r r e g i s t e r ( a d l ) p r e s c a l e r y ( p r e y ) t i m e r y ( t y ) a - d c o n t r o l r e g i s t e r ( a d c o n ) a - d c o n v e r s i o n h i g h - o r d e r r e g i s t e r ( a d h ) i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r ( i n t e d g e ) c p u m o d e r e g i s t e r ( c p u m ) i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 ) i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) p r e s c a l e r 1 2 ( p r e 1 2 ) t i m e r 2 ( t 2 ) p r e s c a l e r x ( p r e x ) t i m e r x ( t x ) t i m e r 1 ( t 1 ) t i m e r x y m o d e r e g i s t e r ( t m ) r e s e r v e d ] m i s r g w a t c h d o g t i m e r c o n t r o l r e g i s t e r ( w d t c o n ) p w m c o n t r o l r e g i s t e r ( p w m c o n ) p w m p r e s c a l e r ( p r e p w m ) p w m r e g i s t e r ( p w m ) t i m e r c o u n t s o u r c e s e l e c t i o n r e g i s t e r ( t c s s ) s e r i a l i / o 2 c o n t r o l r e g i s t e r 1 ( s i o 2 c o n 1 ) s e r i a l i / o 2 c o n t r o l r e g i s t e r 2 ( s i o 2 c o n 2 ) s e r i a l i / o 2 r e g i s t e r ( s i o 2 ) ] r e s e r v e d : d o n o t w r i t e a n y d a t a t o t h i s a d d r e s s e s , b e c a u s e t h e s e a r e a s a r e r e s e r v e d . r e s e r v e d ] r e s e r v e d ] r e s e r v e d ] r e s e r v e d ] r e s e r v e d ] r e s e r v e d ] r e s e r v e d ] r e s e r v e d ] r e s e r v e d ] r e s e r v e d ]
13 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers i/o ports the i/o ports have direction registers which determine the input/ output direction of each individual pin. each bit in a direction register corresponds to one pin, and each pin can be set to be input port or output port. when 0 is written to the bit corresponding to a pin, that pin becomes an input pin. when 1 is written to that bit, that pin becomes an output pin. if data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. pins set to input are floating. if a pin set to input is written to, only the port output latch is written to and the pin remains floating. pin name input/output i/o structure non-port function table 5 i/o port function related sfrs port p0 p0 0 /s in2 p0 1 /s out2 p0 2 /s clk2 p0 3 /s rdy2 port p1 cmos compatible input level cmos 3-state output p0 4 Cp0 7 p1 0 Cp1 7 p2 0 /x cout p2 1 /x cin serial i/o2 function i/o serial i/o2 control register sub-clock generating circuit cpu mode register cmos compatible input level n-channel open-drain output serial i/o1 function i/o serial i/o1 function i/o serial i/o1 function i/o timer x function i/o a-d conversion input serial i/o1 control register serial i/o1 control register serial i/o1 control register timer xy mode register a-d control register timer y function i/o external interrupt input external interrupt input s cmp2 output timer xy mode register interrupt edge selection register interrupt edge selection register serial i/o2 control register cmos compatible input level cmos 3-state output port p2 p2 2 p2 3 input/output, individual bits p2 4 /rxd p2 5 /txd p2 6 /s clk p2 7 /cntr 0 /s rdy1 port p3 port p4 p3 0 /an 0 C p3 4 /an 4 p4 0 /cntr 1 p4 1 /int 0 p4 2 /int 1 p4 3 /int 2 /s cmp2 p4 4 /int 3 /pwm interrupt edge selection register pwm control register external interrupt input pwm output ref.no. (5) (1) (2) (3) (4) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17)
14 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 10 port block diagram (1) p o r t l a t c h ( 1 ) p o r t p 0 0 ( 2 ) p o r t p 0 1 p 0 1 / s o u t 2 p - c h a n n e l o u t p u t d i s a b l e b i t p 0 2 / s c l k 2 p - c h a n n e l o u t p u t d i s a b l e b i t d i r e c t i o n r e g i s t e r p o r t l a t c h d i r e c t i o n r e g i s t e r p o r t l a t c h d i r e c t i o n r e g i s t e r p o r t l a t c h d i r e c t i o n r e g i s t e r p o r t l a t c h d i r e c t i o n r e g i s t e r d i r e c t i o n r e g i s t e r p o r t l a t c h d i r e c t i o n r e g i s t e r p o r t l a t c h d i r e c t i o n r e g i s t e r p o r t l a t c h d a t a b u s d a t a b u s d a t a b u s d a t a b u s d a t a b u s d a t a b u s s e r i a l i / o 2 i n p u t s e r i a l i / o 2 o u t p u t s e r i a l i / o 2 t r a n s m i t c o m p l e t i o n s i g n a l s e r i a l i / o 2 p o r t s e l e c t i o n b i t ( 3 ) p o r t p 0 2 s e r i a l i / o 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t s e r i a l i / o 2 p o r t s e l e c t i o n b i t s e r i a l i / o 2 c l o c k o u t p u t s e r i a l i / o 2 e x t e r n a l c l o c k i n p u t ( 4 ) p o r t p 0 3 s e r i a l i / o 2 r e a d y o u t p u t s r d y 2 o u t p u t e n a b l e b i t ( 5 ) p o r t s p 0 4 - p 0 7 , p 1 ( 6 ) p o r t p 2 0 p o r t x c s w i t c h b i t o s c i l l a t o r p o r t x c s w i t c h b i t p o r t p 2 1 ( 7 ) p o r t p 2 1 p o r t x c s w i t c h b i t d a t a b u s s u b - c l o c k g e n e r a t i n g c i r c u i t i n p u t ( 8 ) p o r t s p 2 2 , p 2 3 d a t a b u s
15 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 11 port block diagram (2) port latch direction register data bus (9) port p2 4 port latch direction register data bus port latch direction register data bus port latch direction register data bus port latch direction register data bus port latch direction register data bus port latch direction register data bus port latch direction register data bus serial i/o1 enable bit receive enable bit serial i/o1 input (11) port p2 6 serial i/o1 synchronous clock selection bit serial i/o1 enable bit serial i/o1 enable bit serial i/o1 mode selection bit serial i/o1 clock output external clock input (13) ports p3 0 -p3 4 a-d converter input analog input pin selection bit (15) ports p4 1 ,p4 2 interrupt input (10) port p2 5 p-channel output disable bit serial i/o1 enable bit transmit enable bit serial i/o1 output (12) port p2 7 serial i/o1 enable bit serial i/o1 mode selection bit pulse output mode s rdy1 output enable bit timer output cntr 0 interrupt input serial ready output pulse output mode (14) port p4 0 timer output cntr 1 interrupt input pulse output mode (16) port p4 3 interrupt input serial i/o2 i/o comparison signal control bit serial i/o2 i/o comparison signal output
16 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 12 port block diagram (3) (17) port p4 4 pwm output data bus pwm output enable bit interrupt input port latch direction register
17 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers interrupts interrupts occur by 14 sources among 14 sources: six external, seven internal, and one software. interrupt control each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software in- terrupt set by the brk instruction. an interrupt occurs if the corresponding interrupt request and enable bits are 1 and the in- terrupt disable flag is 0. interrupt enable bits can be set or cleared by software. interrupt request bits can be cleared by software, but cannot be set by software. the brk instruction cannot be disabled with any flag or bit. the i (interrupt disable) flag disables all interrupts except the brk in- struction interrupt. when several interrupts occur at the same time, the interrupts are received according to priority. interrupt operation by acceptance of an interrupt, the following operations are auto- matically performed: 1. the contents of the program counter and the processor status register are automatically pushed onto the stack. 2. the interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. the interrupt jump destination address is read from the vector table into the program counter. n notes when the active edge of an external interrupt (int 0 Cint 3 , cntr 0 , cntr 1 ) is set, the corresponding interrupt request bit may also be set. therefore, take the following sequence: 1. disable the interrupt 2. change the interrupt edge selection register (the timer xy mode register for cntr 0 and cntr 1 ) 3. clear the interrupt request bit to 0 4. accept the interrupt.
18 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers interrupt request generating conditions remarks interrupt source low fffc 16 high fffd 16 priority 1 table 8 interrupt vector addresses and priority notes 1: vector addresses contain interrupt jump destination addresses. 2: reset function in the same way as an interrupt with the highest priority. vector addresses (note 1) reset (note 2) int 0 reserved int 1 int 2 int 3 / serial i/o2 reserved timer x timer y timer 1 timer 2 serial i/o1 reception serial i/o1 transmission cntr 0 cntr 1 a-d converter brk instruction at reset at detection of either rising or falling edge of int 0 input at detection of either rising or falling edge of int 1 input at detection of either rising or falling edge of int 2 input at detection of either rising or falling edge of int 3 input/ at completion of serial i/o2 data reception/transmission reserved at completion of serial i/o1 data reception at completion of serial i/o1 transfer shift or when transmis- sion buffer is empty at timer x underflow at timer y underflow at timer 1 underflow at timer 2 underflow non-maskable external interrupt (active edge selectable) valid when serial i/o1 is selected valid when serial i/o1 is selected external interrupt (active edge selectable) stp release timer underflow external interrupt (active edge selectable) reserved at detection of either rising or falling edge of cntr 0 input at detection of either rising or falling edge of cntr 1 input at completion of a-d conversion at brk instruction execution external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) switch by serial i/o2/int 3 interrupt source bit fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdc 16 ffdd 16 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 non-maskable software interrupt
19 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 13 interrupt control fig. 14 structure of interrupt-related registers interrupt disable flag (i) interrupt request interrupt request bit interrupt enable bit brk instruction reset b 7 b 0 b 7 b 0 b 7 b 0 b 7 b 0 b 7 b 0 i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r i n t 0 a c t i v e e d g e s e l e c t i o n b i t i n t 1 a c t i v e e d g e s e l e c t i o n b i t i n t 2 a c t i v e e d g e s e l e c t i o n b i t i n t 3 a c t i v e e d g e s e l e c t i o n b i t s e r i a l i / o 2 / i n t 3 i n t e r r u p t s o u r c e b i t 0 : i n t 3 i n t e r r u p t s e l e c t e d 1 : s e r i a l i / o 2 i n t e r r u p t s e l e c t e d n o t u s e d ( r e t u r n s 0 w h e n r e a d ) ( i n t e d g e : a d d r e s s 0 0 3 a 1 6 ) 0 : f a l l i n g e d g e a c t i v e 1 : r i s i n g e d g e a c t i v e i n t e r r u p t r e q u e s t r e g i s t e r 1 i n t 0 i n t e r r u p t r e q u e s t b i t r e s e r v e d i n t 1 i n t e r r u p t r e q u e s t b i t i n t 2 i n t e r r u p t r e q u e s t b i t i n t 3 / s e r i a l i / o 2 i n t e r r u p t r e q u e s t b i t r e s e r v e d t i m e r x i n t e r r u p t r e q u e s t b i t t i m e r y i n t e r r u p t r e q u e s t b i t 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d ( i r e q 1 : a d d r e s s 0 0 3 c 1 6 ) i n t e r r u p t r e q u e s t r e g i s t e r 2 t i m e r 1 i n t e r r u p t r e q u e s t b i t t i m e r 2 i n t e r r u p t r e q u e s t b i t s e r i a l i / o 1 r e c e p t i o n i n t e r r u p t r e q u e s t b i t s e r i a l i / o 1 t r a n s m i t i n t e r r u p t r e q u e s t b i t c n t r 0 i n t e r r u p t r e q u e s t b i t c n t r 1 i n t e r r u p t r e q u e s t b i t a d c o n v e r t e r i n t e r r u p t r e q u e s t b i t n o t u s e d ( r e t u r n s 0 w h e n r e a d ) ( i r e q 2 : a d d r e s s 0 0 3 d 1 6 ) 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d i n t e r r u p t c o n t r o l r e g i s t e r 1 i n t 0 i n t e r r u p t e n a b l e b i t r e s e r v e d ( d o n o t w r i t e 1 t o t h i s b i t . ) i n t 1 i n t e r r u p t e n a b l e b i t i n t 2 i n t e r r u p t e n a b l e b i t i n t 3 / s e r i a l i / o 2 i n t e r r u p t e n a b l e b i t r e s e r v e d ( d o n o t w r i t e 1 t o t h i s b i t . ) t i m e r x i n t e r r u p t e n a b l e b i t t i m e r y i n t e r r u p t e n a b l e b i t ( i c o n 1 : a d d r e s s 0 0 3 e 1 6 ) i n t e r r u p t c o n t r o l r e g i s t e r 2 t i m e r 1 i n t e r r u p t e n a b l e b i t t i m e r 2 i n t e r r u p t e n a b l e b i t s e r i a l i / o 1 r e c e p t i o n i n t e r r u p t e n a b l e b i t s e r i a l i / o 1 t r a n s m i t i n t e r r u p t e n a b l e b i t c n t r 0 i n t e r r u p t e n a b l e b i t c n t r 1 i n t e r r u p t e n a b l e b i t a d c o n v e r t e r i n t e r r u p t e n a b l e b i t n o t u s e d ( r e t u r n s 0 w h e n r e a d ) ( d o n o t w r i t e 1 t o t h i s b i t . ) 0 : i n t e r r u p t s d i s a b l e d 1 : i n t e r r u p t s e n a b l e d ( i c o n 2 : a d d r e s s 0 0 3 f 1 6 ) 0 : i n t e r r u p t s d i s a b l e d 1 : i n t e r r u p t s e n a b l e d
20 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers timers the 3850 group (spec. h) has four timers: timer x, timer y, timer 1, and timer 2. the division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. all timers are count down. when the timer reaches 00 16 , an un- derflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. when a timer underflows, the interrupt request bit corresponding to that timer is set to 1. timer 1 and timer 2 the count source of prescaler 12 is the oscillation frequency which is selected by timer 12 count source selection bit. the out- put of prescaler 12 is counted by timer 1 and timer 2, and a timer underflow sets the interrupt request bit. timer x and timer y timer x and timer y can each select in one of four operating modes by setting the timer xy mode register. (1) timer mode the timer counts the count source selected by timer count source selection bit. (2) pulse output mode the timer counts the count source selected by timer count source selection bit. whenever the contents of the timer reach 00 16 , the signal output from the cntr 0 (or cntr 1 ) pin is inverted. if the cntr 0 (or cntr 1 ) active edge selection bit is 0, output begins at h. if it is 1, output starts at l. when using a timer in this mode, set the corresponding port p2 7 ( or port p4 0 ) direction register to out- put mode. (3) event counter mode operation in event counter mode is the same as in timer mode, except that the timer counts signals input through the cntr 0 or cntr 1 pin. when the cntr 0 (or cntr 1 ) active edge selection bit is 0, the rising edge of the cntr 0 (or cntr 1 ) pin is counted. when the cntr 0 (or cntr 1 ) active edge selection bit is 1, the falling edge of the cntr 0 (or cntr 1 ) pin is counted. (4) pulse width measurement mode if the cntr 0 (or cntr 1 ) active edge selection bit is 0, the timer counts the selected signals by the count source selection bit while the cntr 0 (or cntr 1 ) pin is at h. if the cntr 0 (or cntr 1 ) ac- tive edge selection bit is 1, the timer counts it while the cntr 0 (or cntr 1 ) pin is at l. the count can be stopped by setting 1 to the timer x (or timer y) count stop bit in any mode. the corresponding interrupt request bit is set each time a timer underflows. fig. 15 structure of timer xy mode register n note when switching the count source by the timer 12, x and y count source bit, the value of timer count is altered in unconsiderable amount owing to generating of a thin pulses in the count input signals. therefore, select the timer count source before set the value to the prescaler and the timer. fig. 16 structure of timer count source selection register timer x count stop bit 0: count start 1: count stop timer xy mode register (tm : address 0023 16 ) timer y operating mode bits 0 0: timer mode 0 1: pulse output mode 1 0: event counter mode 1 1: pulse width measurement mode cntr 1 active edge selection bit 0: interrupt at falling edge count at rising edge in event counter mode 1: interrupt at rising edge count at falling edge in event counter mode b7 cntr 0 active edge selection bit 0: interrupt at falling edge count at rising edge in event counter mode 1: interrupt at rising edge count at falling edge in event counter mode b0 timer x operating mode bit 0 0: timer mode 0 1: pulse output mode 1 0: event counter mode 1 1: pulse width measurement mode b1b0 b5b4 timer y count stop bit 0: count start 1: count stop timer count source selection register (tcss : address 0028 16 ) b7 b0 timer x count source selection bit 0 : f(x in )/16 (f(x cin )/16 at low-speed mode) 1 : f(x in )/2 (f(x cin )/2 at low-speed mode) timer y count source selection bit 0 : f(x in )/16 (f(x cin )/16 at low-speed mode) 1 : f(x in )/2 (f(x cin )/2 at low-speed mode) timer 12 count source selection bit 0 : f(x in )/16 (f(x cin )/16 at low-speed mode) 1 : f(x cin ) not used (returns 0 when read)
21 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 17 block diagram of timer x, timer y, timer 1, and timer 2 q q 1 0 p2 7 /cntr 0 q q p4 0 /cntr 1 0 1 r r 1 0 0 1 t t prescaler x latch (8) prescaler x (8) timer x latch (8) timer x (8) to timer x interrupt request bit toggle flip-flop timer x count stop bit pulse width measurement mode event counter mode to cntr 0 interrupt request bit pulse output mode port p2 7 latch port p2 7 direction register cntr 0 active edge selection bit timer x latch write pulse pulse output mode timer mode pulse output mode prescaler y latch (8) prescaler y (8) timer y latch (8) timer y (8) to timer y interrupt request bit toggle flip-flop timer y count stop bit to cntr 1 interrupt request bit pulse output mode port p4 0 latch port p4 0 direction register cntr 1 active edge selection bit timer y latch write pulse pulse output mode timer mode pulse output mode data bus data bus prescaler 12 latch (8) prescaler 12 (8) timer 1 latch (8) timer 1 (8) data bus timer 2 latch (8) timer 2 (8) to timer 2 interrupt request bit to timer 1 interrupt request bit cntr 0 active edge selection bit cntr 1 active edge selection bit pulse width measure- ment mode event counter mode f(x cin ) timer 12 count source selection bit f(x in )/16 f(x in )/2 timer y count source selection bit f(x in )/16 f(x in )/2 timer x count source selection bit f(x in )/16 (f(x cin )/16 at low-speed mode) (f(x cin )/2 at low-speed mode) (f(x cin )/16 at low-speed mode) (f(x cin )/2 at low-speed mode) (f(x cin )/16 at low-speed mode)
22 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers serial i/o1 serial i/o1 can be used as either clock synchronous or asynchro- nous (uart) serial i/o. a dedicated timer is also provided for baud rate generation. (1) clock synchronous serial i/o mode clock synchronous serial i/o mode can be selected by setting the serial i/o1 mode selection bit of the serial i/o1 control register (bit 6 of address 001a 16 ) to 1. for clock synchronous serial i/o, the transmitter and the receiver must use the same clock. if an internal clock is used, transfer is started by a write signal to the tb/rb. fig. 18 block diagram of clock synchronous serial i/o1 fig. 19 operation of clock synchronous serial i/o1 function 1/4 1/4 f/f p2 6 /s clk serial i/o1 status register serial i/o1 control register p2 7 /s rdy1 p2 4 /r x d p2 5 /t x d x in receive buffer register address 0018 16 receive shift register receive buffer full flag (rbf) receive interrupt request (ri) clock control circuit shift clock serial i/o1 synchronous clock selection bit frequency division ratio 1/(n+1) baud rate generator address 001c 16 brg count source selection bit clock control circuit falling-edge detector transmit buffer register data bus address 0018 16 shift clock transmit shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) transmit interrupt source selection bit address 0019 16 data bus address 001a 16 transmit shift register d 7 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 rbf = 1 tsc = 1 tbe = 0 tbe = 1 tsc = 0 transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) serial output txd serial input rxd write pulse to receive/transmit buffer register (address 0018 16 ) overrun error (oe) detection notes 1: as the transmit interrupt (ti), either when the transmit buffer has emptied (tbe=1) or after the transmit shift operation has ended (tsc=1), by setting the transmit interrupt source selection bit (tic) of the serial i/o1 control register. 2: if data is written to the transmit buffer register when tsc=0, the transmit clock is generated continuously and serial data is output continuously from the txd pin. 3: the receive interrupt (ri) is set when the receive buffer full flag (rbf) becomes ??. receive enable signal s rdy1
23 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers (2) asynchronous serial i/o (uart) mode clock asynchronous serial i/o mode (uart) can be selected by clearing the serial i/o1 mode selection bit (b6) of the serial i/o1 control register to 0. eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. the transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. since the shift reg- ister cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. the transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. fig. 20 block diagram of uart serial i/o1 x i n 1 / 4 o e p ef e 1 / 1 6 1 / 1 6 d a t a b u s r e c e i v e b u f f e r r e g i s t e r a d d r e s s 0 0 1 8 1 6 r e c e i v e s h i f t r e g i s t e r r e c e i v e b u f f e r f u l l f l a g ( r b f ) r e c e i v e i n t e r r u p t r e q u e s t ( r i ) b a u d r a t e g e n e r a t o r f r e q u e n c y d i v i s i o n r a t i o 1 / ( n + 1 ) a d d r e s s 0 0 1 c 1 6 s t / s p / p a g e n e r a t o r t r a n s m i t b u f f e r r e g i s t e r d a t a b u s t r a n s m i t s h i f t r e g i s t e r a d d r e s s 0 0 1 8 1 6 t r a n s m i t s h i f t c o m p l e t i o n f l a g ( t s c ) t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) t r a n s m i t i n t e r r u p t r e q u e s t ( t i ) a d d r e s s 0 0 1 9 1 6 s t d e t e c t o r s p d e t e c t o r u a r t c o n t r o l r e g i s t e r a d d r e s s 0 0 1 b 1 6 c h a r a c t e r l e n g t h s e l e c t i o n b i t a d d r e s s 0 0 1 a 1 6 b r g c o u n t s o u r c e s e l e c t i o n b i t t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t s e r i a l i / o s y n c h r o n o u s c l o c k s e l e c t i o n b i t c l o c k c o n t r o l c i r c u i t c h a r a c t e r l e n g t h s e l e c t i o n b i t 7 b i t s 8 b i t s s e r i a l i / o 1 c o n t r o l r e g i s t e r p 2 6 / s c l k s e r i a l i / o 1 s t a t u s r e g i s t e r p 2 4 / r x d p 2 5 / t x d
24 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 21 operation of uart serial i/o1 function [transmit buffer register/receive buffer register (tb/rb)] 0018 16 the transmit buffer register and the receive buffer register are lo- cated at the same address. the transmit buffer is write-only and the receive buffer is read-only. if a character bit length is 7 bits, the msb of data stored in the receive buffer is 0. [serial i/o1 status register (siosts)] 0019 16 the read-only serial i/o1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial i/o1 function and various errors. three of the flags (bits 4 to 6) are valid only in uart mode. the receive buffer full flag (bit 1) is cleared to 0 when the receive buffer register is read. if there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. a write to the serial i/o1 status register clears all the error flags oe, pe, fe, and se (bit 3 to bit 6, respectively). writing 0 to the serial i/o1 enable bit sioe (bit 7 of the serial i/o1 control register) also clears all the status flags, including the error flags. bits 0 to 6 of the serial i/o1 status register are initialized to 0 at reset, but if the transmit enable bit (bit 4) of the serial i/o1 control register has been set to 1, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become 1. [serial i/o1 control register (siocon)] 001a 16 the serial i/o1 control register consists of eight control bits for the serial i/o1 function. [uart control register (uartcon)] 001b 16 the uart control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial i/o is selected and set the data format of an data transfer and one bit (bit 4) which is al- ways valid and sets the output structure of the p2 5 /t x d pin. [baud rate generator (brg)] 001c 16 the baud rate generator determines the baud rate for serial trans- fer. the baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate genera- tor. tsc=0 tbe=1 rbf=0 tbe=0 tbe=0 rbf=1 rbf=1 st d 0 d 1 sp d 0 d 1 st sp tbe=1 tsc=1 st d 0 d 1 sp d 0 d 1 st sp transmit or receive clock transmit buffer write signal generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) 1: error flag detection occurs at the same time that the rbf flag becomes ??(at 1st stop bit, during reception). 2: as the transmit interrupt (ti), when either the tbe or tsc flag becomes ?,? can be selected to occur depending on the settin g of the transmit interrupt source selection bit (tic) of the serial i/o1 control register. 3: the receive interrupt (ri) is set when the rbf flag becomes ?. 4: after data is written to the transmit buffer when tsc=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to tsc=0. notes serial output t x d serial input r x d receive buffer read signal
25 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers b 7 t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) 0 : b u f f e r f u l l 1 : b u f f e r e m p t y r e c e i v e b u f f e r f u l l f l a g ( r b f ) 0 : b u f f e r e m p t y 1 : b u f f e r f u l l t r a n s m i t s h i f t c o m p l e t i o n f l a g ( t s c ) 0 : t r a n s m i t s h i f t i n p r o g r e s s 1 : t r a n s m i t s h i f t c o m p l e t e d o v e r r u n e r r o r f l a g ( o e ) 0 : n o e r r o r 1 : o v e r r u n e r r o r p a r i t y e r r o r f l a g ( p e ) 0 : n o e r r o r 1 : p a r i t y e r r o r f r a m i n g e r r o r f l a g ( f e ) 0 : n o e r r o r 1 : f r a m i n g e r r o r s u m m i n g e r r o r f l a g ( s e ) 0 : ( o e ) u ( p e ) u ( f e ) = 0 1 : ( o e ) u ( p e ) u ( f e ) = 1 n o t u s e d ( r e t u r n s 1 w h e n r e a d ) s e r i a l i / o 1 s t a t u s r e g i s t e r s e r i a l i / o 1 c o n t r o l r e g i s t e r b 7 b 0 b 0 b r g c o u n t s o u r c e s e l e c t i o n b i t ( c s s ) 0 : f ( x i n ) 1 : f ( x i n ) / 4 s e r i a l i / o 1 s y n c h r o n o u s c l o c k s e l e c t i o n b i t ( s c s ) 0 : b r g o u t p u t d i v i d e d b y 4 w h e n c l o c k s y n c h r o n o u s s e r i a l i / o 1 i s s e l e c t e d , b r g o u t p u t d i v i d e d b y 1 6 w h e n u a r t i s s e l e c t e d . 1 : e x t e r n a l c l o c k i n p u t w h e n c l o c k s y n c h r o n o u s s e r i a l i / o 1 i s s e l e c t e d , e x t e r n a l c l o c k i n p u t d i v i d e d b y 1 6 w h e n u a r t i s s e l e c t e d . s r d y 1 o u t p u t e n a b l e b i t ( s r d y ) 0 : p 2 7 p i n o p e r a t e s a s o r d i n a r y i / o p i n 1 : p 2 7 p i n o p e r a t e s a s s r d y 1 o u t p u t p i n t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) 0 : i n t e r r u p t w h e n t r a n s m i t b u f f e r h a s e m p t i e d 1 : i n t e r r u p t w h e n t r a n s m i t s h i f t o p e r a t i o n i s c o m p l e t e d t r a n s m i t e n a b l e b i t ( t e ) 0 : t r a n s m i t d i s a b l e d 1 : t r a n s m i t e n a b l e d r e c e i v e e n a b l e b i t ( r e ) 0 : r e c e i v e d i s a b l e d 1 : r e c e i v e e n a b l e d s e r i a l i / o 1 m o d e s e l e c t i o n b i t ( s i o m ) 0 : c l o c k a s y n c h r o n o u s ( u a r t ) s e r i a l i / o 1 : c l o c k s y n c h r o n o u s s e r i a l i / o s e r i a l i / o 1 e n a b l e b i t ( s i o e ) 0 : s e r i a l i / o 1 d i s a b l e d ( p i n s p 2 4 t o p 2 7 o p e r a t e a s o r d i n a r y i / o p i n s ) 1 : s e r i a l i / o 1 e n a b l e d ( p i n s p 2 4 t o p 2 7 o p e r a t e a s s e r i a l i / o 1 p i n s ) b 7 u a r t c o n t r o l r e g i s t e r c h a r a c t e r l e n g t h s e l e c t i o n b i t ( c h a s ) 0 : 8 b i t s 1 : 7 b i t s p a r i t y e n a b l e b i t ( p a r e ) 0 : p a r i t y c h e c k i n g d i s a b l e d 1 : p a r i t y c h e c k i n g e n a b l e d p a r i t y s e l e c t i o n b i t ( p a r s ) 0 : e v e n p a r i t y 1 : o d d p a r i t y s t o p b i t l e n g t h s e l e c t i o n b i t ( s t p s ) 0 : 1 s t o p b i t 1 : 2 s t o p b i t s p 2 5 / t x d p - c h a n n e l o u t p u t d i s a b l e b i t ( p o f f ) 0 : c m o s o u t p u t ( i n o u t p u t m o d e ) 1 : n - c h a n n e l o p e n d r a i n o u t p u t ( i n o u t p u t m o d e ) n o t u s e d ( r e t u r n 1 w h e n r e a d ) b 0 ( s i o s t s : a d d r e s s 0 0 1 9 1 6 ) ( s i o c o n : a d d r e s s 0 0 1 a 1 6 ) ( u a r t c o n : a d d r e s s 0 0 1 b 1 6 ) fig. 22 structure of serial i/o1 control registers
26 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers serial i/o2 the serial i/o2 can be operated only as the clock synchronous type. as a synchronous clock for serial transfer, either internal clock or external clock can be selected by the serial i/o2 synchronous clock selection bit (b6) of serial i/o2 control register 1. the internal clock incorporates a dedicated divider and permits se- lecting 6 types of clock by the internal synchronous clock selection bits (b2, b1, b0) of serial i/o2 control register 1. regarding s out2 and s clk2 being output pins, either cmos output format or n-channel open-drain output format can be selected by the p0 1 /s out2 , p0 2 /s clk2 p-channel output disable bit (b7) of serial i/o2 control register 1. when the internal clock has been selected, a transfer starts by a write signal to the serial i/o2 register (address 0017 16 ). after comple- tion of data transfer, the level of the s out2 pin goes to high imped- ance automatically but bit 7 of the serial i/o2 control register 2 is not set to 1 automatically. when the external clock has been selected, the contents of the serial i/o2 register is continuously sifted while transfer clocks are input. accordingly, control the clock externally. note that the s out2 pin does not go to high impedance after completion of data transfer. to cause the s out2 pin to go to high impedance in the case where the external clock is selected, set bit 7 of the serial i/o2 control reg- ister 2 to 1 when s clk2 is h after completion of data transfer. after the next data transfer is started (the transfer clock falls), bit 7 of the serial i/o2 control register 2 is set to 0 and the s out2 pin is put into the active state. regardless of the internal clock to external clock, the interrupt re- quest bit is set after the number of bits (1 to 8 bits) selected by the optional transfer bit is transferred. in case of a fractional number of bits less than 8 bits as the last data, the received data to be stored in the serial i/o2 register becomes a fractional number of bits close to msb if the transfer direction selection bit of serial i/o2 control regis- ter 1 is lsb first, or a fractional number of bits close to lsb if the said bit is msb first. for the remaining bits, the previously received data is shifted. at transmit operation using the clock synchronous serial i/o, the s cmp2 signal can be output by comparing the state of the transmit pin s out2 with the state of the receive pin s in2 in synchronization with a rise of the transfer clock. if the output level of the s out2 pin is equal to the input level to the s in2 pin, l is output from the s cmp2 pin. if not, h is output. at this time, an int 2 interrupt request can also be gener- ated. select a valid edge by bit 2 of the interrupt edge selection reg- ister (address 003a 16 ). [serial i/o2 control registers 1, 2 (sio2con1 / sio2con2)] 0015 16, 0016 16 the serial i/o2 control registers 1 and 2 are containing various se- lection bits for serial i/o2 control as shown in figure 23. fig. 23 structure of serial i/o2 control registers 1, 2 s e r i a l i / o 2 c o n t r o l r e g i s t e r 1 ( s i o 2 c o n 1 : a d d r e s s 0 0 1 5 1 6 ) s e r i a l i / o 2 c o n t r o l r e g i s t e r 2 ( s i o 2 c o n 2 : a d d r e s s 0 0 1 6 1 6 ) b 7 b 0 o p t i o n a l t r a n s f e r b i t s b 2 b 1 b 0 0 0 0 : 1 b i t 0 0 1 : 2 b i t 0 1 0 : 3 b i t 0 1 1 : 4 b i t 1 0 0 : 5 b i t 1 0 1 : 6 b i t 1 1 0 : 7 b i t 1 1 1 : 8 b i t n o t u s e d ( r e t u r n s " 0 " w h e n r e a d ) s e r i a l i / o 2 i / o c o m p a r i s o n s i g n a l c o n t r o l b i t 0 : p 4 3 i / o 1 : s c m p 2 o u t p u t s o u t 2 p i n c o n t r o l b i t ( p 0 1 ) 0 : o u t p u t a c t i v e 1 : o u t p u t h i g h - i m p e d a n c e i n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s b 2 b 1 b 0 0 0 0 : f ( x i n ) / 8 ( f ( x c i n ) / 8 i n l o w - s p e e d m o d e ) 0 0 1 : f ( x i n ) / 1 6 ( f ( x c i n ) / 1 6 i n l o w - s p e e d m o d e ) 0 1 0 : f ( x i n ) / 3 2 ( f ( x c i n ) / 3 2 i n l o w - s p e e d m o d e ) 0 1 1 : f ( x i n ) / 6 4 ( f ( x c i n ) / 6 4 i n l o w - s p e e d m o d e ) 1 1 0 : f ( x i n ) / 1 2 8 f ( x c i n ) / 1 2 8 i n l o w - s p e e d m o d e ) 1 1 1 : f ( x i n ) / 2 5 6 ( f ( x c i n ) / 2 5 6 i n l o w - s p e e d m o d e ) s e r i a l i / o 2 p o r t s e l e c t i o n b i t 0 : i / o p o r t 1 : s o u t 2 , s c l k 2 o u t p u t p i n s r d y 2 o u t p u t e n a b l e b i t 0 : p 0 3 p i n i s n o r m al i / o p i n 1 : p 0 3 p i n i s s r d y 2 o u t p u t p i n t r a n s f e r d i r e c t i o n s e l e c t i o n b i t 0 : l s b f i r s t 1 : m s b f i r s t s e r i a l i / o 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t 0 : e x t e r n a l c l o c k 1 : i n t e r n a l c l o c k p 0 1 / s o u t 2 , p 0 2 / s c l k 2 p - c h a n n e l o u t p u t d i s a b l e b i t 0 : c m o s o u t p u t ( i n o u t p u t m o d e ) 1 : n - c h a n n e l o p e n - d r a i n o u t p u t ( i n o u t p u t m o d e ) b 7 b 0
27 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 24 block diagram of serial i/o2 fig. 25 timing chart of serial i/o2 x i n 1 0 0 1 0 1 s r d y 2 s c l k 2 0 1 1 / 8 1 / 1 6 1 / 3 2 1 / 6 4 1 / 1 2 8 1 / 2 5 6 1 0 x c i n 1 0 0 0 0 1 d a t a b u s s e r i a l i / o 2 i n t e r r u p t r e q u e s t s e r i a l i / o 2 p o r t s e l e c t i o n b i t s e r i a l i / o c o u n t e r 2 ( 3 ) s e r i a l i / o 2 r e g i s t e r ( 8 ) s y n c h r o n o u s c i r c u i t s e r i a l i / o 2 p o r t s e l e c t i o n b i t s e r i a l i / o 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t s r d y 2 o u t p u t e n a b l e b i t e x t e r n a l c l o c k i n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t d i v i d e r o p t i o n a l t r a n s f e r b i t s ( 3 ) p 0 2 / s c l k 2 p 0 1 / s o u t 2 p 0 0 / s i n 2 p 0 2 l a t c h p 0 1 l a t c h p 0 3 l a t c h p 0 3 / s r d y 2 p 4 3 / s c m p 2 / i n t 2 s e r i a l i / o 2 i / o c o m p a r i s o n s i g n a l c o n t r o l b i t p 4 3 l a t c h q d m a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t s ( n o t e ) n o t e : e i t h e r h i g h - s p e e d , m i d d l e - s p e e d o r l o w - s p e e d m o d e i s s e l e c t e d b y b i t s 6 a n d 7 o f c p u m o d e r e g i s t e r . d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 t r a n s f e r c l o c k ( n o t e 1 ) s e r i a l i / o 2 o u t p u t s o u t 2 s e r i a l i / o 2 i n p u t s i n 2 r e c e i v e e n a b l e s i g n a l s r d y 2 w r i t e - i n s i g n a l t o s e r i a l i / o 2 r e g i s t e r ( n o t e 2 ) s e r i a l i / o 2 i n t e r r u p t r e q u e s t b i t s e t . 1 : w h e n t h e i n t e r n a l c l o c k i s s e l e c t e d a s a t r a n s f e r c l o c k , t h e f ( x i n ) c l o c k d i v i s i o n ( f ( x c i n ) i n l o w - s p e e d m o d e ) c a n b e s e l e c t e d b y s e t t i n g b i t s 0 t o 2 o f s e r i a l i / o 2 c o n t r o l r e g i s t e r 1 . 2 : w h e n t h e i n t e r n a l c l o c k i s s e l e c t e d a s a t r a n s f e r c l o c k , t h e s o u t 2 p i n h a s h i g h i m p e d a n c e a f t e r t r a n s f e r c o m p l e t i o n . n o t e s
28 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 26 s cmp2 output operation s clk2 s in2 s out2 s cmp2 judgement of i/o data comparison
29 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers pulse width modulation (pwm) the 3850 group (spec. h) has a pwm function with an 8-bit resolution, based on a signal that is the clock input x in or that clock input divided by 2. data setting the pwm output pin also functions as port p4 4 . set the pwm period by the pwm prescaler, and set the h term of output pulse by the pwm register. if the value in the pwm prescaler is n and the value in the pwm register is m (where n = 0 to 255 and m = 0 to 255) : pwm period = 255 5 (n+1) / f(x in ) = 31.875 5 (n+1) m s (when f(x in ) = 8 mhz,count source selection bit = 0) output pulse h term = pwm period 5 m / 255 = 0.125 5 (n+1) 5 m m s (when f(x in ) = 8 mhz,count source selection bit = 0) fig. 27 timing of pwm period fig. 28 block diagram of pwm function pwm operation when bit 0 (pwm enable bit) of the pwm control register is set to 1, operation starts by initializing the pwm output circuit, and pulses are output starting at an h. if the pwm register or pwm prescaler is updated during pwm output, the pulses will change in the cycle after the one in which the change was made. 31.875 5 m 5 (n+1) 255 m s t = [31.875 5 (n+1)] m s pwm output m: contents of pwm register n : contents of pwm prescaler t : pwm period (when f(x in ) = 8 mhz,count source selection bit = ?? data bus count source selection bit ? ? pwm prescaler pre-latch pwm register pre-latch pwm prescaler latch pwm register latch transfer control circuit pwm register 1/2 x in port p4 4 latch pwm enable bit port p4 4 pwm prescaler (x cin at low-speed mode)
30 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 29 structure of pwm control register fig. 30 pwm output timing when pwm register or pwm prescaler is changed n note the pwm starts after the pwm function enable bit is set to enable and l level is output from the pwm pin. the length of this l level output is as follows: sec (count source selection bit = 0, where n is the value set in the prescaler) sec (count source selection bit = 1, where n is the value set in the prescaler) n+1 2 ? f(x in ) n+1 f(x in ) pwm control register (pwmcon : address 001d 16 ) pwm function enable bit count source selection bit not used (return 0 when read) b7 b0 0: pwm disabled 1: pwm enabled 0: f(x in ) (f(x cin ) at low-speed mode) 1: f(x in )/2 (f(x cin )/2 at low-speed mode) abc b t c t2 = pwm output pwm register write signal pwm prescaler write signal (changes h term from a to b.) (changes pwm period from t to t2.) when the contents of the pwm register or pwm prescaler have changed, the pwm output will change from the next period after the change. t t t2
31 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers a-d converter [a-d conversion registers (adl, adh)] 0035 16 , 0036 16 the a-d conversion registers are read-only registers that store the result of an a-d conversion. do not read these registers during an a-d conversion. [ad control register (adcon)] 0034 16 the ad control register controls the a-d conversion process. bits 0 to 2 select a specific analog input pin. bit 4 indicates the completion of an a-d conversion. the value of this bit remains at 0 during an a-d conversion and changes to 1 when an a-d conversion ends. writing 0 to this bit starts the a-d conversion. comparison voltage generator the comparison voltage generator divides the voltage between av ss and v ref into 1024 and outputs the divided voltages. channel selector the channel selector selects one of ports p3 0 /an 0 to p3 4 /an 4 and inputs the voltage to the comparator. comparator and control circuit the comparator and control circuit compare an analog input volt- age with the comparison voltage, and the result is stored in the a-d conversion registers. when an a-d conversion is completed, the control circuit sets the a-d conversion completion bit and the a-d interrupt request bit to 1. note that because the comparator consists of a capacitor cou- pling, set f(x in ) to 500 khz or more during an a-d conversion. when the a-d converter is operated at low-speed mode, f(x in ) and f(x cin ) do not have the lower limit of frequency, because of the a-d converter has a built-in self-oscillation circuit. fig. 31 structure of ad control register fig. 32 structure of a-d conversion registers fig. 33 block diagram of a-d converter ad control register (adcon : address 0034 16 ) analog input pin selection bits 0 0 0: p3 0 /an 0 0 0 1: p3 1 /an 1 0 1 0: p3 2 /an 2 0 1 1: p3 3 /an 3 1 0 0: p3 4 /an 4 not used (returns 0 when read) a-d conversion completion bit 0: conversion in progress 1: conversion completed not used (returns 0 when read) b7 b0 b2 b1 b0 10-bit reading (read address 0036 16 before 0035 16 ) (address 0036 16 ) (address 0035 16 ) 8-bit reading (read only address 0035 16 ) (address 0035 16 ) b8 b7 b6 b5 b4 b3 b2 b1 b0 b7 b0 b9 b7 b0 note : the high-order 6 bits of address 0036 16 become ? at reading. b9 b8 b7 b6 b5 b4 b3 b2 b7 b0 channel selector a-d control circuit a-d conversion low-order register resistor ladder v ref av ss comparator a-d interrupt request b7 b0 3 10 p3 0 /an 0 p3 1 /an 1 p3 2 /an 2 p3 3 /an 3 p3 4 /an 4 data bus ad control register a-d conversion high-order register (address 0034 16 ) (address 0036 16 ) (address 0035 16 )
32 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers watchdog timer the watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, be- cause of a software run-away). the watchdog timer consists of an 8-bit watchdog timer l and an 8-bit watchdog timer h. standard operation of watchdog timer when any data is not written into the watchdog timer control reg- ister (address 0039 16 ) after reset, the watchdog timer is in the stop state. the watchdog timer starts to count down by writing an optional value into the watchdog timer control register (address 0039 16 ) and an internal reset occurs at an underflow of the watch- dog timer h. accordingly, programming is usually performed so that writing to the watchdog timer control register (address 0039 16 ) may be started before an underflow. when the watchdog timer control reg- ister (address 0039 16 ) is read, the values of the high-order 6 bits of the watchdog timer h, stp instruction disable bit, and watch- dog timer h count source selection bit are read. l initial value of watchdog timer at reset or writing to the watchdog timer control register (address 0039 16 ), each watchdog timer h and l is set to ff 16 . fig. 35 structure of watchdog timer control register l watchdog timer h count source selection bit operation bit 7 of the watchdog timer control register (address 0039 16 ) per- mits selecting a watchdog timer h count source. when this bit is set to 0, the count source becomes the underflow signal of watchdog timer l. the detection time is set to 131.072 ms at f(x in ) = 8 mhz frequency and 32.768 s at f(x cin ) = 32 khz frequency. when this bit is set to 1, the count source becomes the signal divided by 16 for f(x in ) (or f(x cin )). the detection time in this case is set to 512 m s at f(x in ) = 8 mhz frequency and 128 ms at f(x cin ) = 32 khz frequency. this bit is cleared to 0 after reset. l operation of stp instruction disable bit bit 6 of the watchdog timer control register (address 0039 16 ) per- mits disabling the stp instruction when the watchdog timer is in operation. when this bit is 0, the stp instruction is enabled. when this bit is 1, the stp instruction is disabled, once the stp instruction is executed, an internal reset occurs. when this bit is set to 1, it cannot be rewritten to 0 by program. this bit is cleared to 0 after reset. fig. 34 block diagram of watchdog timer x in data bus x cin 10 00 01 main clock division ratio selection bits (note) ? ? 1/16 watchdog timer h count source selection bit reset circuit stp instruction disable bit watchdog timer h (8) ?f 16 ?is set when watchdog timer control register is written to. internal reset reset watchdog timer l (8) note: any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the cpu mode register. stp instruction ?f 16 ?is set when watchdog timer control register is written to. b0 stp instruction disable bit 0: stp instruction enabled 1: stp instruction disabled watchdog timer h count source selection bit 0: watchdog timer l underflow 1: f(x in )/16 or f(x cin )/16 watchdog timer h (for read-out of high-order 6 bit) watchdog timer control register (wdtcon : address 0039 16 ) b7
33 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers reset circuit to reset the microcomputer, reset pin must be held at an "l" level for 2 m s or more. then the reset pin is returned to an "h" level (the power source voltage must be between 2.7 v and 5.5 v, and the oscillation must be stable), reset is released. after the re- set is completed, the program starts from the address contained in address fffd 16 (high-order byte) and address fffc 16 (low-order byte). make sure that the reset input voltage is less than 0.54 v for v cc of 2.7 v. fig. 37 reset sequence fig. 36 reset circuit example (note) 0.2v cc 0v 0v poweron v cc reset v cc reset power source voltage detection circuit power source voltage reset input voltage note : reset release voltage ; vcc=2.7 v reset data f address sync x in : 8 to 13 clock cycles x in ? ? ? ? ? fffc fffd ad h , l ? ? ? ? ? ad l ad h 1: the frequency relation of f(x in ) and f( f ) is f(x in ) = 2 f( f ). 2: the question marks (?) indicate an undefined state that depends on the previous state. 3: all signals except x in and reset are internals. reset address from the vector table. notes reset out
34 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 38 internal status at reset note : x : not fixed since the initial values for other than above mentioned registers and ram contents are indefinite at reset, they must be set. (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (29) (30) (31) (32) (33) address register contents 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 ff 16 01 16 00 16 00 16 ff 16 ff 16 ff 16 ff 16 00 16 port p0 (p0) port p0 direction register (p0d) port p1 (p1) port p1 direction register (p1d) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p3 direction register (p3d) port p4 (p4) port p4 direction register (p4d) serial i/o2 control register 1 (sio2con1) serial i/o2 control register 2 (sio2con2) serial i/o2 register (sio2) transmit/receive buffer register (tb/rb) serial i/o1 status register (siosts) serial i/o1 control register (siocon) uart control register (uartcon) baud rate generator (brg) pwm control register (pwmcon) pwm prescaler (prepwm) pwm register (pwm) prescaler 12 (pre12) timer 1 (t1) timer 2 (t2) timer xy mode register (tm) prescaler x (prex) timer x (tx) prescaler y (prey) timer y (ty) timer count source selection register (tcss) a-d control register (adcon) a-d conversion low-order register (adl) a-d conversion high-order register (adh) 0000 0111 1000 0000 xxxxxxxx 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0034 16 0035 16 0036 16 1110 0000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0001 0000 xxxxxxxx xx 00 16 00 16 00 16 00 16 00 16 00 16 (34) (35) (36) (37) (38) (39) (40) (41) (42) (43) register contents 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 (ps) (pc h ) (pc l ) address xxxxx1xx fffd 16 contents fffc 16 contents 00111111 01001000 misrg watchdog timer control register (wdtcon) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 1 (icon1) interrupt control register 2 (icon2) processor status register program counter 000000
35 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers clock generating circuit the 3850 group (spec. h) has two built-in oscillation circuits. an oscillation circuit can be formed by connecting a resonator be- tween x in and x out (x cin and x cout ). use the circuit constants in accordance with the resonator manufacturers recommended values. no external resistor is needed between x in and x out since a feed-back resistor exists on-chip. however, an external feed-back resistor is needed between x cin and x cout . immediately after power on, only the x in oscillation circuit starts oscillating, and x cin and x cout pins function as i/o ports. frequency control (1) middle-speed mode the internal clock f is the frequency of x in divided by 8. after re- set, this mode is selected. (2) high-speed mode the internal clock f is half the frequency of x in . (3) low-speed mode the internal clock f is half the frequency of x cin . n note if you switch the mode between middle/high-speed and low- speed, stabilize both x in and x cin oscillations. the sufficient time is required for the sub-clock to stabilize, especially immediately af- ter power on and at returning from the stop mode. when switching the mode between middle/high-speed and low-speed, set the fre- quency on condition that f(x in ) > 3?f(x cin ). (4) low power dissipation mode the low power consumption operation can be realized by stopping the main clock x in in low-speed mode. to stop the main clock, set bit 5 of the cpu mode register to 1. when the main clock x in is restarted (by setting the main clock stop bit to 0), set sufficient time for oscillation to stabilize. the sub-clock x cin -x cout oscillating circuit can not directly input clocks that are generated externally. accordingly, make sure to cause an external resonator to oscillate. oscillation control (1) stop mode if the stp instruction is executed, the internal clock f stops at an h level, and x in and x cin oscillation stops. when the oscillation stabilizing time set after stp instruction released bit is 0, the prescaler 12 is set to ff 16 and timer 1 is set to 01 16 . when the oscillation stabilizing time set after stp instruction released bit is 1, set the sufficient time for oscillation of used oscillator to stabi- lize since nothing is set to the prescaler 12 and timer 1. either x in or x cin divided by 16 is input to the prescaler 12 as count source. oscillator restarts when an external interrupt is re- ceived, but the internal clock f is not supplied to the cpu (remains at h) until timer 1 underflows. the internal clock f is supplied for the first time, when timer 1 underflows. this ensures time for the clock oscillation using the ceramic resonators to be stabilized. when the oscillator is restarted by reset, apply l level to the reset pin until the oscillation is stable since a wait time will not be generated. fig. 39 ceramic resonator circuit fig. 40 external clock input circuit (2) wait mode if the wit instruction is executed, the internal clock f stops at an h level, but the oscillator does not stop. the internal clock f re- starts at reset or when an interrupt is received. since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. to ensure that the interrupts will be received to release the stp or wit state, their interrupt enable bits must be set to 1 before ex- ecuting of the stp or wit instruction. when releasing the stp state, the prescaler 12 and timer 1 will start counting the clock x in divided by 16. accordingly, set the timer 1 interrupt enable bit to 0 before executing the stp instruc- tion. n note when using the oscillation stabilizing time set after stp instruction released bit set to 1, evaluate time to stabilize oscillation of the used oscillator and set the value to the timer 1 and prescaler 12. x cin x cout x in x out c in c out c cin c cout rf rd x cin x cout x in x out c cin c cout rf rd open external oscillation circuit vcc vss
36 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 41 structure of misrg [misrg (misrg)] 0038 16 misrg consists of three control bits (bits 1 to 3) for middle-speed mode automatic switch and one control bit (bit 0) for oscillation stabilizing time set after stp instruction released. by setting the middle-speed mode automatic switch start bit to 1 while operating in the low-speed mode and setting the middle- speed mode automatic switch set bit to 1, x in oscillation automatically starts and the mode is automatically switched to the middle-speed mode. fig. 42 system clock generating circuit block diagram (single-chip mode) misrg (misrg : address 0038 16 ) oscillation stabilizing time set after stp instruction released bit 0: automatically set 01 16 to timer 1, ff 16 to prescaler 12 1: automatically set nothing b7 b0 note: when the mode is automatically switched from the low-speed mode to the middle-speed mode, the value of cpu mode register (address 003b 16 ) changes. not used (return 0 when read) middle-speed mode automatic switch start bit (depending on program) 0: invalid 1: automatic switch start middle-speed mode automatic switch wait time set bit 0: 4.5 to 5.5 machine cycles 1: 6.5 to 7.5 machine cycles middle-speed mode automatic switch set bit 0: not set automatically 1: automatic switching enable wit instruction stp instruction timing f (internal clock) s r q stp instruction s r q main clock stop bit s r q 1/2 1/4 x in x out x cout x cin interrupt request reset interrupt disable flag l 1/2 port x c switch bit 1 0 low-speed mode high-speed or middle-speed mode middle-speed mode high-speed or low-speed mode main clock division ratio selection bits (note 1) notes 1: any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the cpu mode register. when low-speed mode is selected, set port xc switch bit (b1) to ?? 2: when bit 0 of misrg = ? main clock division ratio selection bits (note 1) ff 16 01 16 prescaler 12 timer 1 reset or stp instruction (note 2)
37 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 43 state transitions of system clock c m 4 : p o r t x c s w i t c h b i t 0 : i / o p o r t f u n c t i o n ( s t o p o s c i l l a t i n g ) 1 : x c i n - x c o u t o s c i l l a t i n g f u n c t i o n c m 5 : m a i n c l o c k ( x i n - x o u t ) s t o p b i t 0 : o p e r a t i n g 1 : s t o p p e d c m 7 , c m 6 : m a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t b 7 b 6 0 0 : f = f ( x i n ) / 2 ( h i g h - s p e e d m o d e ) 0 1 : f = f ( x i n ) / 8 ( m i d d l e - s p e e d m o d e ) 1 0 : f = f ( x c i n ) / 2 ( l o w - s p e e d m o d e ) 1 1 : n o t a v a i l a b l e n o t e s r e s e t c m 4 1 ?? 0 c m 4 0 ?? 1 c m 6 1 ?? 0 c m 4 1 ?? 0 c m 6 1 ?? 0 c m 7 1 ?? 0 c m 4 1 ?? 0 c m 5 1 ?? 0 c m 6 1 ?? 0 c m 6 1 ?? 0 c p u m o d e r e g i s t e r b 7b 4 c m 7 0 ?? 1 c m 6 1 ?? 0 ( c p u m : a d d r e s s 0 0 3 b 1 6 ) c m 7 = 0 c m 6 = 1 c m 5 = 0 ( 8 m h z o s c i l l a t i n g ) c m 4 = 0 ( 3 2 k h z s t o p p e d ) m i d d l e - s p e e d m o d e ( f ( f ) = 1 m h z ) c m 7 = 0 c m 6 = 1 c m 5 = 0 ( 8 m h z o s c i l l a t i n g ) c m 4 = 1 ( 3 2 k h z o s c i l l a t i n g ) m i d d l e - s p e e d m o d e ( f ( f ) = 1 m h z ) c m 7 = 0 c m 6 = 0 c m 5 = 0 ( 8 m h z o s c i l l a t i n g ) c m 4 = 0 ( 3 2 k h z s t o p p e d ) h i g h - s p e e d m o d e ( f ( f ) = 4 m h z ) c m 7 = 1 c m 6 = 0 c m 5 = 0 ( 8 m h z o s c i l l a t i n g ) c m 4 = 1 ( 3 2 k h z o s c i l l a t i n g ) l o w - s p e e d m o d e ( f ( f ) = 1 6 k h z ) c m 7 = 1 c m 6 = 0 c m 5 = 1 ( 8 m h z s t o p p e d ) c m 4 = 1 ( 3 2 k h z o s c i l l a t i n g ) l o w - s p e e d m o d e ( f ( f ) = 1 6 k h z ) c m 7 = 0 c m 6 = 0 c m 5 = 0 ( 8 m h z o s c i l l a t i n g ) c m 4 = 1 ( 3 2 k h z o s c i l l a t i n g ) h i g h - s p e e d m o d e ( f ( f ) = 4 m h z ) 1 : s w i t c h t h e m o d e b y t h e a l l o w s s h o w n b e t w e e n t h e m o d e b l o c k s . ( d o n o t s w i t c h b e t w e e n t h e m o d e s d i r e c t l y w i t h o u t a n a l l o w . ) 2 : t h e a l l m o d e s c a n b e s w i t c h e d t o t h e s t o p m o d e o r t h e w a i t m o d e a n d r e t u r n t o t h e s o u r c e m o d e w h e n t h e s t o p m o d e o r t h e w a i t m o d e i s e n d e d . 3 : t i m e r o p e r a t e s i n t h e w a i t m o d e . 4 : w h e n b i t 0 o f m i s r g i s 0 a n d t h e s t o p m o d e i s e n d e d , a d e l a y o f a p p r o x i m a t e l y 1 m s o c c u r s b y c o n n e c t i n g t i m e r 1 i n m i d d l e / h i g h - s p e e d m o d e . 5 : w h e n b i t 0 o f m i s r g i s 0 a n d t h e s t o p m o d e i s e n d e d , t h e f o l l o w i n g i s p e r f o r m e d . ( 1 ) a f t e r t h e c l o c k i s r e s t a r t e d , a d e l a y o f a p p r o x i m a t e l y 2 5 6 m s o c c u r s i n l o w - s p e e d m o d e i f t i m e r 1 2 c o u n t s o u r c e s e l e c t i o n b i t i s 0 . ( 2 ) a f t e r t h e c l o c k i s r e s t a r t e d , a d e l a y o f a p p r o x i m a t e l y 1 6 m s o c c u r s i n l o w - s p e e d m o d e i f t i m e r 1 2 c o u n t s o u r c e s e l e c t i o n b i t i s 1 . 6 : w a i t u n t i l o s c i l l a t i o n s t a b i l i z e s a f t e r o s c i l l a t i n g t h e m a i n c l o c k x i n b e f o r e t h e s w i t c h i n g f r o m t h e l o w - s p e e d m o d e t o m i d d l e / h i g h - s p e e d m o d e . 7 : t h e e x a m p l e a s s u m e s t h a t 8 m h z i s b e i n g a p p l i e d t o t h e x i n p i n a n d 3 2 k h z t o t h e x c i n p i n . f i n d i c a t e s t h e i n t e r n a l c l o c k .
38 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers notes on programming processor status register the contents of the processor status register (ps) after a reset are undefined, except for the interrupt disable flag (i) which is 1. af- ter a reset, initialize flags which affect program execution. in particular, it is essential to initialize the index x mode (t) and the decimal mode (d) flags because of their effect on calculations. interrupts the contents of the interrupt request bits do not change immedi- ately after they have been written. after writing to an interrupt request register, execute at least one instruction before perform- ing a bbc or bbs instruction. decimal calculations ? to calculate in decimal notation, set the decimal mode flag (d) to 1, then execute an adc or sbc instruction. after executing an adc or sbc instruction, execute at least one instruction be- fore executing a sec, clc, or cld instruction. ? in decimal mode, the values of the negative (n), overflow (v), and zero (z) flags are invalid. timers if a value n (between 0 and 255) is written to a timer latch, the fre- quency division ratio is 1/(n+1). multiplication and division instructions ? the index x mode (t) and the decimal mode (d) flags do not af- fect the mul and div instruction. ? the execution of these instructions does not change the con- tents of the processor status register. ports the contents of the port direction registers cannot be read. the following cannot be used: ? the data transfer instruction (lda, etc.) ? the operation instruction when the index x mode flag (t) is 1 ? the addressing mode which uses the value of a direction regis- ter as an index ? the bit-test instruction (bbc or bbs, etc.) to a direction register ? the read-modify-write instructions (ror, clb, or seb, etc.) to a direction register. use instructions such as ldm and sta, etc., to set the port direc- tion registers. serial i/o in clock synchronous serial i/o, if the receive side is using an ex- ternal clock and it is to output the s rdy1 signal, set the transmit enable bit, the receive enable bit, and the s rdy1 output enable bit to 1. serial i/o1 continues to output the final bit from the t x d pin after transmission is completed. s out2 pin for serial i/o2 goes to high impedance after transmis- sion is completed. when an external clock is used as synchronous clock in serial i/ o1 or serial i/o2, write transmission data to the transmit buffer register or serial i/o2 register while the transfer clock is h. a-d converter the comparator uses capacitive coupling amplifier whose charge will be lost if the clock frequency is too low. therefore, make sure that f(x in ) in the middle/high-speed mode is at least on 500 khz during an a-d conversion. do not execute the stp or wit instruction during an a-d conver- sion. instruction execution time the instruction execution time is obtained by multiplying the fre- quency of the internal clock f by the number of cycles needed to execute an instruction. the number of cycles required to execute an instruction is shown in the list of machine instructions. the frequency of the internal clock f is half of the x in frequency in high-speed mode. notes on usage differences between 3850 group (standard) and 3850 group (spec. h) (1) the absolute maximum ratings of 3850 group (spec. h) is smaller than that of 3850 group (standard). ?power source voltage vcc = C0.3 to 6.5 v ?cnvss input voltage v i = C0.3 to vcc +0.3 v (2) the oscillation circuit constants of x in -x out , x cin -x cout may be some differences between 3850 group (standard) and 3850 group (spec. h). (3) do not write any data to the reserved area and the reserved bit. (do not change the contents after rest.) (4) fix bit 3 of the cpu mode register to 1. (5) be sure to perform the termination of unused pins. handling of source pins in order to avoid a latch-up occurrence, connect a capacitor suit- able for high frequencies as bypass capacitor between power source pin (v cc pin) and gnd pin (v ss pin) and between power source pin (v cc pin) and analog power source input pin (av ss pin). besides, connect the capacitor to as close as possible. for bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 m fC0.1 m f is recom- mended.
39 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers v cc v ss v ref av ss v ia v ih v ih v il v il v il electrical characteristics table 7 absolute maximum ratings power source voltage input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 , p2 1, p2 4 Cp2 7 , p3 0 Cp3 4 , p4 0 Cp4 4 , v ref input voltage p2 2 , p2 3 input voltage reset, x in input voltage cnv ss output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 , p2 1, p2 4 Cp2 7 , p3 0 Cp3 4 , p4 0 Cp4 4 , x out output voltage p2 2 , p2 3 power dissipation operating temperature storage temperature v cc v i v i v i v i v o v o p d t opr t stg symbol parameter conditions ratings C0.3 to 6.5 C0.3 to v cc +0.3 C0.3 to 5.8 C0.3 to v cc +0.3 C0.3 to v cc +0.3 C0.3 to v cc +0.3 C0.3 to 5.8 1000 (note) C20 to 85 C40 to 125 v v v v v v v mw c c unit t a = 25 c all voltages are based on v ss . output transistors are cut off. 5.5 5.5 v cc v cc v cc v cc 0.2v cc 0.2v cc 0.16v cc power source voltage power source voltage a-d convert reference voltage analog power source voltage analog input voltage an 0 Can 4 h input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 4 , p4 0 Cp4 4 h input voltage reset, x in , cnv ss l input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 4 , p4 0 Cp4 4 l input voltage reset, cnv ss l input voltage x in symbol parameter limits min. unit table 8 recommended operating conditions (1) (v cc = 2.7 to 5.5 v, t a = C20 to 85 c, unless otherwise noted) 4.0 2.7 2.0 av ss 0.8v cc 0.8v cc 0 0 0 5.0 5.0 0 0 typ. max. C80 C80 80 120 80 C40 C40 40 60 40 h total peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p3 0 Cp3 4 (note) h total peak output current p2 0 , p2 1 , p2 4 Cp2 7 , p4 0 Cp4 4 (note) l total peak output current (note) p0 0 Cp0 7 , p3 0 Cp3 4 l total peak output current (note) p1 0 Cp1 7 l total peak output current p2 0 Cp2 7 ,p4 0 Cp4 4 (note) h total average output current p0 0 Cp0 7 , p1 0 Cp1 7 , p3 0 Cp3 4 (note) h total average output current p2 0 , p2 1 , p2 4 Cp2 7 , p4 0 Cp4 4 (note) l total average output current (note) p0 0 Cp0 7 , p3 0 Cp3 4 l total average output current (note) p1 0 Cp1 7 l total average output current p2 0 Cp2 7 ,p4 0 Cp4 4 (note) s i oh(peak) s i oh(peak) s i ol(peak) s i ol(peak) s i ol(peak) s i oh(avg) s i oh(avg) s i ol(avg) s i ol(avg) s i ol(avg) ma ma ma ma ma ma ma ma ma ma note : the total output current is the sum of all the currents flowing through all the applicable ports. the total average current is an average value measured over 100 ms. the total peak current is the peak value of all the currents. v v v v v v v v v v note : the rating becomes 300mw at the 42p2r-a/e package. 8 mhz (high-speed mode) 8 mhz (middle-speed mode), 4 mhz (high-speed mode)
40 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers table 9 recommended operating conditions (2) (v cc = 2.7 to 5.5 v, t a = C20 to 85 c, unless otherwise noted) C10 10 20 C5 5 15 8 4 h peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 , p2 1 , p2 4 Cp2 7 , p3 0 Cp3 4 , p4 0 Cp4 4 (note 1) l peak output current (note 1) p0 0 Cp0 7 , p2 0 Cp2 7 , p3 0 Cp3 4 , p4 0 Cp4 4 l peak output current (note 1) p1 0 Cp1 7 h average output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 , p2 1 , p2 4 Cp2 7 , p3 0 Cp3 4 , p4 0 Cp4 4 (note 2) l average output current (note 2) p0 0 Cp0 7 , p2 0 Cp2 7 , p3 0 Cp3 4 , p4 0 Cp4 4 l average output current (note 2) p1 0 Cp1 7 internal clock oscillation frequency (v cc = 4.0 to 5.5v) (note 3) internal clock oscillation frequency (v cc = 2.7 to 5.5v) (note 3) i oh(peak) i ol(peak) i ol(peak) i oh(avg) i ol(avg) i ol(avg) f(x in ) f(x in ) symbol parameter limits min. ma ma ma ma ma ma mhz mhz unit typ. max. notes 1: the peak output current is the peak current flowing in each port. 2: the average output current i ol (avg), i oh (avg) are average value measured over 100 ms. 3: when the oscillation frequency has a duty cycle of 50%.
41 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers table 10 electrical characteristics (1) (v cc = 2.7 to 5.5 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) h output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 , p2 1, p2 4 Cp2 7 , p3 0 Cp3 4 , p4 0 Cp4 4 (note) l output voltage p0 0 Cp0 7 , p2 0 Cp2 7, p3 0 Cp3 4 , p4 0 Cp4 4 l output voltage p1 0 Cp1 7 hysteresis cntr 0 , cntr 1 , int 0 Cint 3 hysteresis rxd, s clk hysteresis ____________ reset h input current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 , p2 1, p2 4 Cp2 7 , p3 0 Cp3 4 , p4 0 Cp4 4 h input current ____________ reset, cnv ss h input current x in l input current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 p3 0 Cp3 4 , p4 0 Cp4 4 l input current ____________ reset,cnv ss l input current x in ram hold voltage limits v v v v v v v v v m a m a m a m a m a m a v parameter min. typ. max. symbol unit note: p2 5 is measured when the p2 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0. i oh = C10 ma v cc = 4.0C5.5 v i oh = C1.0 ma v cc = 2.7C5.5 v i ol = 10 ma v cc = 4.0C5.5 v i ol = 1.0 ma v cc = 2.7C5.5 v i ol = 20 ma v cc = 4.0C5.5 v i ol = 10 ma v cc = 2.7C5.5 v v i = v cc v i = v cc v i = v cc v i = v ss v i = v ss v i = v ss when clock stopped v cc C2.0 v cc C1.0 2.0 test conditions 0.4 0.5 0.5 4 C4 2.0 1.0 2.0 1.0 5.0 5.0 C5.0 C5.0 5.5 v oh v ol v ol v t+ Cv tC v t+ Cv tC v t+ Cv tC i ih i ih i ih i il i il i il v ram
42 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers table 11 electrical characteristics (2) (v cc = 2.7 to 5.5 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) power source current limits parameter min. typ. max. symbol unit high-speed mode f(x in ) = 8 mhz f(x cin ) = 32.768 khz output transistors off high-speed mode f(x in ) = 8 mhz (in wit state) f(x cin ) = 32.768 khz output transistors off low-speed mode f(x in ) = stopped f(x cin ) = 32.768 khz output transistors off low-speed mode f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors off low-speed mode (v cc = 3 v) f(x in ) = stopped f(x cin ) = 32.768 khz output transistors off low-speed mode (v cc = 3 v) f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors off middle-speed mode f(x in ) = 8 mhz f(x cin ) = stopped output transistors off middle-speed mode f(x in ) = 8 mhz (in wit state) f(x cin ) = stopped output transistors off increment when a-d conversion is executed f(x in ) = 8 mhz test conditions 13 i cc ta = 25 c ta = 85 c 6.8 ma all oscillation stopped (in stp state) output transistors off 1.6 60 20 20 5.0 4.0 1.5 800 0.1 200 40 55 10.0 7.0 1.0 10 ma m a m a m a m a ma ma m a m a m a
43 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers bit lsb 2tc(x in ) m s k w m a m a resolution absolute accuracy (excluding quantization error) conversion time ladder resistor reference power source input current a-d port input current min. 50 typ. 40 35 150 0.5 max. 10 4 61 200 5.0 5.0 high-speed mode, middle-speed mode low-speed mode v ref = 5.0 v table 12 a-d converter characteristics (v cc = 2.7 to 5.5 v, v ss = av ss = 0 v, t a = C20 to 85 c, f(x in ) = 8 mhz, unless otherwise noted) unit limits parameter C C t conv r ladder i vref i i(ad) test conditions symbol v ref on v ref off
44 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers timing requirements table 13 timing requirements (1) (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) reset input l pulse width external clock input cycle time external clock input h pulse width external clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 to int 3 input h pulse width int 0 to int 3 input l pulse width serial i/o1 clock input cycle time (note) t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (cntr) t wh (cntr) t wl (cntr) t wh (int) t wl (int) t c (s clk1 ) t wh (s clk1 ) t wl (s clk1 ) t su (r x d-s clk1 ) t h (s clk1 -r x d) t c (s clk2 ) t wh (s clk2 ) t wl (s clk2 ) t su (s in2 -s clk2 ) t h (s clk2 -s in2 ) limits m s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns parameter min. 2 125 50 50 200 80 80 80 80 800 370 370 220 100 1000 400 400 200 200 typ. max. symbol unit note : when f(x in ) = 8 mhz and bit 6 of address 001a 16 is 1 (clock synchronous). divide this value by four when f(x in ) = 8 mhz and bit 6 of address 001a 16 is 0 (uart). serial i/o1 clock input h pulse width (note) serial i/o1 clock input l pulse width (note) serial i/o1 input setup time serial i/o1 input hold time serial i/o2 clock input cycle time serial i/o2 clock input h pulse width serial i/o2 clock input l pulse width serial i/o2 clock input setup time serial i/o2 clock input hold time table 14 timing requirements (2) (v cc = 2.7 to 5.5 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) reset input l pulse width external clock input cycle time external clock input h pulse width external clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 to int 3 input h pulse width int 0 to int 3 input l pulse width serial i/o1 clock input cycle time (note) serial i/o1 clock input h pulse width (note) serial i/o1 clock input l pulse width (note) serial i/o1 input setup time serial i/o1 input hold time serial i/o2 clock input cycle time serial i/o2 clock input h pulse width serial i/o2 clock input l pulse width serial i/o2 clock input setup time serial i/o2 clock input hold time t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (cntr) t wh (cntr) t wl (cntr) t wh (int) t wl (int) t c (s clk1 ) t wh (s clk1 ) t wl (s clk1 ) t su (r x d-s clk1 ) t h (s clk1 -r x d) t c (s clk2 ) t wh (s clk2 ) t wl (s clk2 ) t su (s in2 -s clk2 ) t h (s clk2 -s in2 ) limits m s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns parameter min. 2 250 100 100 500 230 230 230 230 2000 950 950 400 200 2000 950 950 400 300 typ. max. symbol unit note : when f(x in ) = 4 mhz and bit 6 of address 001a 16 is 1 (clock synchronous). divide this value by four when f(x in ) = 4 mhz and bit 6 of address 001a 16 is 0 (uart).
45 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers table 15 switching characteristics (1) (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) serial i/o1 clock output h pulse width serial i/o1 clock output l pulse width serial i/o1 output delay time (note 1) serial i/o1 output valid time (note 1) serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output h pulse width serial i/o2 clock output l pulse width serial i/o2 output delay time (note 2) serial i/o2 output valid time (note 2) serial i/o2 clock output falling time cmos output rising time (note 3) cmos output falling time (note 3) t wh (s clk1 ) t wl (s clk1 ) t d (s clk1 -t x d) t v (s clk1 -t x d) t r (s clk1 ) t f (s clk1 ) t wh (s clk2 ) t wl (s clk2 ) t d (s clk2 -s out2 ) t v (s clk2 -s out2 ) t f (s clk2 ) t r (cmos) t f (cmos) limits ns ns ns ns ns ns ns ns ns ns ns ns ns parameter min. t c (s clk1 )/2C30 t c (s clk1 )/2C30 C30 t c (s clk2 )/2C160 t c (s clk2 )/2C160 0 typ. 10 10 max. 140 30 30 200 30 30 30 symbol unit notes 1: when the p2 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0. 2: when the p0 1 /s out2 and p0 2 /s clk2 p-channel output disable bit of the serial i/o2 control register 1 (bit 7 of address 0015 16 ) is 0. 3: the x out pin is excluded. test conditions fig.44 table 16 switching characteristics (2) (v cc = 2.7 to 5.5 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) serial i/o1 clock output h pulse width serial i/o1 clock output l pulse width serial i/o1 output delay time (note 1) serial i/o1 output valid time (note 1) serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output h pulse width serial i/o2 clock output l pulse width serial i/o2 output delay time (note 2) serial i/o2 output valid time (note 2) serial i/o2 clock output falling time cmos output rising time (note 3) cmos output falling time (note 3) t wh (s clk1 ) t wl (s clk1 ) t d (s clk1 -t x d) t v (s clk1 -t x d) t r (s clk1 ) t f (s clk1 ) t wh (s clk2 ) t wl (s clk2 ) t d (s clk2 -s out2 ) t v (s clk2 -s out2 ) t f (s clk2 ) t r (cmos) t f (cmos) limits ns ns ns ns ns ns ns ns ns ns ns ns ns parameter min. t c (s clk1 )/2C50 t c (s clk1 )/2C50 C30 t c (s clk2 )/2C240 t c (s clk2 )/2C240 0 typ. 20 20 max. 350 50 50 400 50 50 50 symbol unit notes 1: when the p2 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0. 2: when the p0 1 /s out2 and p0 2 /s clk2 p-channel output disable bit of the serial i/o2 control register 1 (bit 7 of address 0015 16 ) is 0. 3: the x out pin is excluded. test conditions fig.44
46 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 44 circuit for measuring output switching characteristics measurement output pin 100pf cmos output
47 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 45 timing diagram t c(cntr) 0.2v cc t wl(int) 0.8v cc t wh(int) 0.2v cc 0.8v cc t w(reset) reset 0.2v cc t wl(cntr) 0.8v cc t wh(cntr) 0.2v cc 0.2v cc 0.8v cc 0.8v cc 0.2v cc t wl(x in ) 0.8v cc t wh(x in ) t c(x in ) x in t f t r t d(s clk1 -t x d), t d(s clk2 -s out2 ) t v(s clk1 -t x d), t v(s clk2 -s out2 ) t c(s clk1 ), t c(s clk2 ) t wl(s clk1 ), t wl(s clk2 ) t wh(s clk1 ), t wh(s clk2 ) t h(s clk1 - r x d), t h(s clk2 - s in2 ) t su(r x d - s clk1 ), t su(s in2 - s clk2 ) t x d s out2 r x d s in2 s clk1 s clk2 int 0 to int 3 cntr 0 cntr 1
48 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers package outline sdip42-p-600-1.78 weight(g) C jedec code 4.1 eiaj package code lead material alloy 42/cu alloy 42p4b plastic 42pin 600mil sdip symbol min nom max a a 2 b b 1 b 2 c e d l dimension in millimeters a 1 0.51 ?.8 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 36.5 36.7 36.9 12.85 13.0 13.15 1.778 15.24 3.0 0 e15 e e 5.5 e e 1 42 22 21 1 e c e 1 a 2 a 1 b b 1 b 2 e l a seating plane d ssop42-p-450-0.80 weight(g) e jedec code 0.63 eiaj package code lead material alloy 42 42p2r-a/e plastic 42pin 450mil ssop symbol min nom max a a 2 b c d e l l 1 y dimension in millimeters h e a 1 i 2 .25 0 .05 0 .13 0 .3 17 .2 8 .63 11 .3 0 .27 1 .0 2 .3 0 .15 0 .5 17 .4 8 .8 0 .93 11 .5 0 .765 1 .43 11 .4 2 .4 0 .2 0 .7 17 .6 8 .23 12 .7 0 .15 0 b 2 ?5 0 0 e10 e e 1 42 22 21 1 h e e d e y f a a 2 a 1 l 1 l c e b 2 e 1 i 2 recommended mount pad detail f z z 1 detail g e e z 1 0.75 e e 0.9 z b g
49 3850 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers wdip42-c-600-1.78 weight(g) jedec code eiaj package code 42s1b-a metal seal 42pin 600mil dip 0.46 0.25 3.44 15.8 3.05 symbol min nom max a a 2 b b 1 c d e l z dimension in millimeters a 1 3.05 15.24 1.778 41.1 0.33 0.17 0.9 0.8 0.7 0.54 0.38 1.0 5.0 e e 1 e e d 1 42 22 21 b z seating plane a l a 2 a 1 b 1 e 1 c
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rev. rev. no. date 1.0 first edition 000309 1.1 font errors are revised. 000322 revision description list 3850 group (spec. h) data sheet (1/1) revision description

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